Magnetic random access memory (MRAM) is a type of non-volatile memory that uses magnetism rather than electrical power to store data. Key attributes of MRAM technology are nonvolatility and unlimited read and program endurance. Conventional MRAM cells are described in U.S. patent application Ser. No. 10/907,977, entitled “Magnetic Random Access Memory Device,” by Jhon Jhy Liaw, and is herein incorporated by reference for all purposes. Also pertinent as background to this invention is U.S. patent application Ser. No. 11/150,014, entitled “Multiple Stage Method and System for Sensing Outputs from Memory Cells,” filed Jun. 13, 2005, by Jhon Jhy Liaw, and is also herein incorporated by reference for all purposes.
A fundamental issue for MRAM technology is the sensing scheme for reading data from a magnetoresistive element within an MRAM cell. Conventional schemes have several limitations and drawbacks. One such limitation that affects reliability is caused by temperature and process-induced disparities in the Magneto-Resistance (MR) ratio of cells. Since cells may perform differently when a potential is applied to them, and known read schemes have limited sensing margins, there may be errors in detecting the state of the data stored in the magnetoresistive element. For example, a known sense amplifier design is provided by H. S. Jeong et al., in a paper entitled “Fully Integrated 64 Kb MRAM with Novel Reference Cell Scheme,” ISBN 0-7803-7463-X (2002). In this conventional sense amplifier design, a reference current Iref is generated by averaging Imax cell current and Imin cell current (i.e., Iref=(Imax+Imin)/2). The read current through a selected cell is compared with the reference current by a current sense amplifier circuit. In Jeong's read scheme, the maximum sensing margin is half of the MR ratio (1/2 MR), with around a ten to twenty percent differential margin. With process and operational fluctuations, such as disparities in magnetoresistance element area, MR ratio, temperature effects, MOSFET characteristics, et cetera, the final sensing margin may be lower than 0% and thereby result in a read fail.
Another limitation is that of speed in reading data. Currently, logic circuits are operating at frequencies in the GHz ranges. However, conventional MRAM read schemes are constrained to operate at much slower rates, causing a significant performance gap between the logic circuits and the MRAM memory. This performance gap results in a suboptimal performance of the logic circuits because supporting MRAM memory devices cannot provide data and instructions fast enough. Thus, this results in a bottleneck effect at the MRAM devices, particularly in System on Chip (SoC) designs, which combine memory with logic circuitry on a chip.
Thus, sensing the resistance state of an MRAM memory cell can be unreliable. It would therefore be desirable to more reliably sense the resistance states of memory cells in MRAM devices, and to improve the speed of MRAM data read access.